Commodore Amiga A500 Technical Reference Manual page 176

FIFO Access
(F7)
This state opens a path t o an internal FlFO that is 64 bytes in length.
The falling edge of PCSD- will start t o shift data out of the FlFO for a
read or shift data into the FlFO on the rising edge of PCSD- if the
RIW- was set low with LD2. The DMA will initiate host memory ac-
cess, done a word at a time, whenever the FlFO is half full. A typical
memory access without any wait states takes 4 cycles, each cycle be-
ing about 1 4 0 ns.
Read DMA Status (EF)
The host DMA status must be read before initiating any data trans-
fer, since its FlFO can be shared by another device. At the end of ev-
ery word or block transfer initiated by the hard disk controller, the
status must be read t o ensure successful data transfer completion.
Status is not read after every word in a block transfer. After the last
byte, in a block transfer, has been strobed into the DMA controller
approximately 12 US are needed t o ensure that the DMA status lines
are all high. To read the status, any number of PCSD- strobes may be
used before initiating another DMA cycle. The DMA internal status
available after the falling edge of PCSD- is interpreted as follows:
DATA BIT
7:
This line will be high if no DMA was requested o r
a DMA cycle was completed. After completion of
a word o r a block transfer, this bit will be set
high. A low indicates DMA busy status.
DATA BIT 6: This bit is high if a byte of data
is
available t o be
read from the FIFO, or if there is a byte t o be
written and the FlFO is not full. At the end of a
block write operation t o the disk, since there are
no more bytes available, this bit is set low.
DATA BIT 5:
This line is low if the FlFO overflowed or
underflowed. This may occur during a disk
transfer if the DMA circuit does not receive a bus
acknowledge signal from another device on the
68000 motherboard, before the FIFO becomes
full or empty. Under this condition the FlFO is
cleared by the 280, before any other data
transfer can be initiated.
DATA BITS 4-0:
These data lines will be logic zero.
Reset IREQ- (9F) This state will force IREQ- line t o high impedance. It is set low by the
host.