Commodore Amiga A500 Technical Reference Manual page 38

The collision circuit also monitors A23 through A1 9 and OVR* on the
bus, so that the internal reserved address spaces of the Amiga can be
checked. An access to any of the internal address spaces will make
the Amiga respond as the slave unless OVR* (override) is asserted.
Any two slave responses on the same cycle constitute a collision.
Refer to the COLLISION PAL equation in Table 3-5 for this discus-
sion.
Generating the
PROC
Before generating the collision detection equation, we must make
Term
the equation that detects whether the Amiga processor board is re-
sponding to this cycle as a slave. This signal is called PROC internally
to the PAL. While it comes out on pin 18, it is not used external to
the PAL.
The term BAS
*
/A23
*
/A22
*
/A21
*
/RESET
*
/OVR will be true
when the processor board memory is responding to the 2 megabyte
space starting at hex 000000.
Similarly, the next term will be true when the processor board is re-
sponding to the 2 megabyte space that starts at hex A00000.
The next term detects the processor board responding to the 2
megabyte space starting at C00000.
The next term detects the processor board responding to the 112
megabyte space starting at E00000.
And the last term detects the proc board responding to the 112,
megabyte space starting at F80000. This takes care of all the spaces
used by the processor board.
Generating NOTCOL[S
Why the inverted name? We would have preferred to call this signal
/
COLLISION but our PAL assembler does not allow a NOT sign
in
the
name on the left side of the equal sign. NOTCOLIS goes out through
the output inverter and becomes/NOTCOLIS which is logically equiv-
alent to NOTNOTCOLIS
=
COLLISION, so NOTCOLIS being true
inside the PAL will make COLLISION false outside the PAL.
Now that PROC will tell us when the responding slave is inside the
Amiga, we are ready to do collision detection.
In our example, we have seven possible slaves to keep track of. They
are the Amiga board (PROC), five PlCs on this backplane, and
SLAVEIN* from the upstream backplane or device. If six of the seven
are inactive at all times, we know that no two are active at the same
time.
Because the slave lines go inactive between bus cycles, there should
not be a case of one slave going active before the previous one went
inactive.