Commodore Amiga A500 Technical Reference Manual page 174

H O S T INTERFACE
PROTOCOL
Interface Protocol
DMA Commands
The host interface is via a
DMA
controller. This DMA device is con-
trolled by the Z80A on the disk controller board or
68000
(host). On
the host side there are counters for the address bus that are preset
before the beginning of each transfer. Three bytes must be written
for the 2 3 address lines (A23-AI). The MSB (corresponding to A24)
of the upper address latch is used to control the host WW- line for
DMA
transfers. This line is set high to read from the host memory
and low
if
a write is intended. The
DMA
logic, contained in one chip,
can be configured to transfer a single word (2 bytes) or
256
words
(51 2 bytes). Transfer are always on even byte boundaries.
The method of communicating to the
DMA
circuit is by two control
lines PCSS- and PCSD-, controlled by the 280 or 68000. PCSS- is al-
ways strobed first to strobe in the "state" on the data bus. The state
will determine the function to be performed on the succeeding
PCSD- strobes. Not all valid states need to be followed by a PSCD-
strobe and for each state loaded, PCSD- can be strobed any number
of times. When reading the host status for instance, the expected
number of PCSD- strobes need not be given, but when writing to the
DMA
controller the correct number of PCSD- strobes must always be
given.
The valid commands, for
DMA
operations, are summarized in the ta-
ble below.
All
data values are listed in hex.
Multiple states can be strobed into he
DMA
controller as long as no
bus contention occurs. Notice that the state bits 4-0 are low in one
position only for all the valid states. This implies that any state that
does not require transfer of data by the following PCSD- can be
combined and set simultaneously. Hence a single word transfer and
start
DMA
cycle can be combined as
DE.
Some states are mutually ex-
clusive such as F7 (transfer data to or from the FIFO) and EF (read-
ing the DMA status). Similarly state
D 6
is illegal since word transfer
and the FIFO path open will result in BUS contention. State FC is per-
mitted as long as the same data is to be written in the
DMA
mid ad-
dress latch and
DMA
low address counter. Other such valid states can
be similarly derived.