Phase Locked Loop - Motorola MC9S12C-Family User Manual

time t . The device features a clock monitor. A time-out is asserted if the frequency of the incoming
UPOSC
clock signal is below the Clock Monitor FailureAssert Frequency f
Conditions are shown in Table A-4 unless otherwise noted
Num C
1a C Crystal oscillator range (Colpitts)
1b C
Crystal oscillator range (Pierce)
2 P Startup Current
3 C Oscillator start-up time (Colpitts)
4 D Clock Quality check time-out
5 P Clock Monitor Failure Assert Frequency
6 P
External square wave input frequency
7 D External square wave pulse width low
8 D External square wave pulse width high
9 D External square wave rise time
10 D External square wave fall time
11 D Input Capacitance (EXTAL, XTAL pins)
DC Operating Bias in Colpitts Configuration
12 C
on EXTAL Pin
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. f = 4MHz, C = 22pF.
osc
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset
B.6.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
B.6.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Table B-11 Oscillator Characteristics
Rating
1(4)
4
Device User Guide — 9S12C128DGV1/D V01.05
CMFA.
Symbol Min
f
0.5
OSC
f
0.5
OSC
i
100
OSC
t
UPOSC
t
0.45
CQOUT
f
50
CMFA
f
0.5
EXT
t
9.5
EXTL
t
9.5
EXTH
t
EXTR
t
EXTF
C
IN
V
DCBIAS
Typ Max Unit
16 MHz
40 MHz
A
2 3
ms
8 100
2.5 s
100 200 KHz
50 MHz
ns
ns
1 ns
1 ns
7 pF
1.1 V
111