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Device User Guide — 9S12C128DGV1/D V01.05
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V
Num C
Reference Potential
1
D
2
C Differential Reference Voltage
3
D ATD Clock Frequency
ATD 10-Bit Conversion Period
4
D
Conv, Time at 2.0MHz ATD Clock f
ATD 8-Bit Conversion Period
5
D
Conv, Time at 2.0MHz ATD Clock f
D Recovery Time (V
6
7
P
Reference Supply current
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
B.4.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influenceon the
accuracy of the ATD.
B.4.3.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowable.
B.4.3.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage 1LSB, then the external filter capacitor, C
100
Table B-4 ATD Operating Characteristics
Rating
Clock Cycles
Clock Cycles
=3.3 Volts)
DDA
Symbol
Min
V
V
Low
RL
SSA
High
V
V
RH
DDA
V
-V
3.0
RH
RL
f
0.5
ATDCLK
1
N
14
CONV10
T
7
ATDCLK
CONV10
(1)
N
12
CONV8
T
6
ATDCLK
CONV8
t
REC
I
REF
1024 * (C
- C
f
INS
<= 3.3V+10%
DDA
Typ
Max
V
DDA
/2
V
DDA
3.3
3.6
2.0
28
14
26
13
20
0.250
).
INN
Unit
/2
V
V
V
MHz
Cycles
s
Cycles
s
s
mA
S
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