Figure C-2 Spi Master Timing (Cpha=1) - Motorola MC9S12C-Family User Manual

Device User Guide — 9S12C128DGV1/D V01.05
1
SS
(OUTPUT)
SCK
(CPOL 0)
(OUTPUT)
SCK
(CPOL 1)
(OUTPUT)
MISO
(INPUT)
9
MOSI
PORT DATA
(OUTPUT)
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
In Table C-2 the timing characteristics for master mode are listed.
Num C
1 P SCK Frequency
1 P SCK Period
2 D Enable Lead Time
3 D Enable Lag Time
4 D Clock (SCK) High or Low Time
5 D Data Setup Time (Inputs)
6 D Data Hold Time (Inputs)
9 D Data Valid after SCK Edge
10 D Data Valid after SS fall (CPHA=0)
11 D Data Hold Time (Outputs)
12 D Rise and Fall Time Inputs
13 D Rise and Fall Time Outputs
120
1
2
4
4
5 6
2
MSB IN
2
MASTER MSB OUT

Figure C-2 SPI Master Timing (CPHA=1)

Table C-2 SPI Master Mode Timing Characteristics
Characteristic
12 13
12 13
BIT 6 . . . 1
11
BIT 6 . . . 1 MASTER LSB OUT
Symbol
Min
f
1/2048
sck
t
2
sck
t
—
lead
t
—
lag
t
—
wsck
t
8
su
t
8
hi
t
—
vsck
t
—
vss
t
20
ho
t
—
rfi
t
—
rfo
3
LSB IN
PORT DATA
Typ Max
— 1 2
— 2048
1/2 —
1/2 —
1/2 —
— —
— —
— 30
— 15
— —
— 8
— 8
Unit
f
bus
t
bus
t
sck
t
sck
t
sck
ns
ns
ns
ns
ns
ns
ns