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And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
=10kHz:
C
2
R
=
---------------------------- -
The capacitance C
can now be calculated as:
s
C
s
The capacitance C
should be chosen in the range of:
p
B.6.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock f
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.
f
VCO
n
=
------------ -
=
2
f
ref
n f
C
= 2* *50*10kHz/(316.7Hz/ )=9.9k =~10k
K
2
0.516
2
=
--------------------- -
-------------- -
f
f
R
C
C
C
20 C
s
p
is measured and input voltage to the VCO is adjusted
ref
Device User Guide — 9S12C128DGV1/D V01.05
synr
+
1
= 50
= 5.19nF =~ 4.7nF
;
=
0.9
R
C
10
C
= 470pF
s
p
, the
cmp
113
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