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Device User Guide — 9S12C128DGV1/D V01.05
f
osc
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
, f
and i
1
1
ch
The grey boxes show the calculation for f
for f
= 4MHz and a 25MHz bus clock.
OSC
The VCO Gain at the desired VCO frequency is approximated by:
K
V
The phase detector relationship is given by:
i
is the current in tracking mode.
ch
The loop bandwidth f
C
typical values are 50. = 0.9 ensures a good transient response.
f
112
VDDPLL
f
1
ref
refdv+1
Figure B-3 Basic PLL functional diagram
from Table B-12.
VCO
f
–
f
1
vco
---------------------- -
K
1V
1
=
K
e
=
1
K
=
i
K
–
ch
should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10,
2
f
ref
<
------------------------------------------
C
+
1
+
C
p
R
C
s
Phase
K
Detector
f
cmp
Loop Divider
1
synr+1
= 50MHz and f
= 1MHz. E.g., these frequencies are used
ref
60 50
–
----------------------- -
100
–
100
e
= -90.48MHz/V
–
= 316.7Hz/
V
f
1
ref
f
<
------------- -
----- -
C
10
4 10
2
f
< 25kHz
C
XFC Pin
VCO
K
V
1
2
0.9
;
=
f
vco
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