Spi; Appendix C Electrical Specifications; Master Mode; Figure C-1 Spi Master Timing (Cpha=0) - Motorola MC9S12C-Family User Manual

B.8 SPI

Appendix C Electrical Specifications

This section provides electrical parametrics and ratings for the SPI.
In Table C-1 the measurement conditions are listed.
Description
Drive mode
Load capacitance C
LOAD,
on all outputs
Thresholds for delay
measurement points

C.1 Master Mode

In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.
1
SS
(OUTPUT)
2
SCK
(CPOL 0)
(OUTPUT)
SCK
(CPOL 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Table C-1 Measurement Conditions
(20% / 80%) VDDX
1
4
4
5 6
2
MSB IN BIT 6 . . . 1
10 9
2
BIT 6 . . . 1
MSB OUT

Figure C-1 SPI Master Timing (CPHA=0)

Device User Guide — 9S12C128DGV1/D V01.05
Value
full drive mode
50
12
12
LSB IN
LSB OUT
Unit
—
pF
V
13 3
13
11
119