Figure C-8 Mii Port Timing Model - Sun Microsystems Ultra 60 Service Manual

illustrates MII being used to interconnect both integrated circuits and
FIGURE C-8
circuit assemblies. This enables separate signal transmission paths to exist between
the reconciliation sublayer, embedded in the Cheerio ASIC, and a local PHY IC, and
between the reconciliation sublayer and a remote PHY IC. The unidirectional paths
between the reconciliation sublayer and the local PHY IC are composed of sections
A1, B1, C1 and D1. The unidirectional paths between the reconciliation sublayer and
the remote PHY IC are composed of sections A2, B2, C2, and D2.
Reconciliation
sublayer
( )
Cheerio ASIC
MII Port Timing Model
FIGURE C-8
A2
A1 B1
PHY
(local)
D1 C1
D2
Appendix C Functional Description
B2
PHY
(remote)
C2
C-27