Sun Microsystems Ultra 60 Service Manual page 50

CODE EXAMPLE 3-2
2> <00> FPU ASI Access Test
2> <00> Dcache RAM Test
2> <00> Dcache Tag Test
2> <00> Icache RAM Test
2> <00> Icache Tag Test
2> <00> Icache Next Test
2> <00> Icache Predecode Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
0> <1f> PIO Write Error, Target Abort Test
0> <1f> Timer Increment Test
0> <1f> Consistent DMA UE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> Init Memory
0> <00> Memory Addr w/ Ecache Test
0>INFO:128MB Bank 0
0>INFO:
0>INFO:
0>INFO:
0> <00> Block Memory Addr Test
0>INFO:128MB Bank 0
0>INFO:
0>INFO:
0>INFO:
0> <00> ECC Memory Addr Test
0>INFO:128MB Bank 0
0>INFO:
0>INFO:
0>INFO:
0> <00> Memory Status Test
0>INFO:128MB Bank 0
0>INFO:
0>INFO:
0>INFO:
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
2> <00> V9 Instruction Test
2> <00> CPU Tick and Tick Compare Reg Test
0> <1f> Init Psycho
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
3-16 Sun Ultra 60 Service Manual • August 2001
diag-level Variable Set to min
0MB Bank 1
0MB Bank 2
0MB Bank 3
0MB Bank 1
0MB Bank 2
0MB Bank 3
0MB Bank 1
0MB Bank 2
0MB Bank 3
0MB Bank 1
0MB Bank 2
0MB Bank 3
(Continued)