332 Mhz Smp Nodes; 332 Mhz Smp Node System Architecture - IBM RS/6000 SP Handbook

2.8 332 MHz SMP nodes

On April 21, 1998, IBM first introduced the PCI-based nodes, the RS/6000 SP
332 MHz SMP thin nodes and wide nodes. They provide two or four way
symmetric multiprocessing (SMP) utilizing PowerPC technology and extend the
RS/6000 PCI I/O technology to the SP system.

2.8.1 332 MHz SMP node system architecture

The 332 MHz SMP node is designed as a bus-based symmetric multiprocessor
(SMP) using a 64-bit address and a 128-bit data system bus running at a 2:1
processor clock ratio. Attached to the system bus are from one to four PowerPC
604e processors with dedicated, in-line L2 cache/bus converter chips and a two
chip memory-I/O controller. Note that the 604e processor only uses a 32-bit
address bus. The memory-I/O controller generates an independent, separately
clocked mezzanine I/O bridge bus to which multiple chips can be attached to
implement various architected I/O buses (for example, PCI) that also operate
independently and are separately clocked.
This design partitions all the system logic into a high speed processor-memory
portion and a lower speed I/O portion. This has the cost advantage of not having
to design I/O bridges to run wide buses at high speeds and it also removes
electrical loading on the SMP system bus, which allows that bus to run even
faster. The wide, high speed processor-memory bus reduces memory and
intervention latency, while the separate I/O bridge bus supports memory
coherent I/O bridges on a narrower, more cost effective bus. The memory-I/O
controller performs all coherency checking for the I/O on the SMP system bus
but relieves the SMP system bus from all I/O data traffic.
Figure 2-6 on page 62 shows the 332 MHz SMP node system architecture block
diagram.
Chapter 2. SP internal processor nodes
61