System Firmware And Rtas; Dynamic Processor Deallocation; 375 Mhz Power3 Smp High Node - IBM RS/6000 SP Handbook
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2.2.5 System firmware and RTAS
The 375 MHz POWER3 SMP node system firmware flash memory is located on
the I/O planar. System firmware contains code that is executed by the 375 MHz
POWER3 microprocessor during the initial program load (IPL) phase of the
system boot. It also supports various interactions between the AIX operating
system and hardware. The extent and method of interaction is defined in the
RS/6000 Platform Architecture (RPA). The Run Time Abstraction Software
(RTAS) defined by RPA provides support for AIX and hardware for specific
functions such as initialization, power management, time of day, I/O
configuration, and capture and display of hardware indicators. RTAS and system
IPL code are contained on 1 MB of flash memory.
2.2.6 Dynamic processor deallocation
Another high availability feature is processor deallocation. This feature allows the
system to completely isolate a processor that has been determined to be
operating below an acceptable level of reliability. To accomplish this, the system
monitors processor status in real time to determine when the number of
recoverable errors has exceeded a specified threshold. When the threshold is
exceeded, the system sends a report to the operating environment that a
processor is unreliable. The AIX operating environment then re-routes all
interrupts and processes to other processors and disables the unreliable
processor complex without interrupting end user services. The last available
Firmware is recommended to be installed on the 375 MHz Node. The Web site
where microcode/firmware can be downloaded from is located at:
http://www.austin.ibm.com/support/micro/download.html
2.2.7 375 MHz POWER3 SMP High Node
Table 2-1 outlines the 375 MHz POWER3 High Node and Figure 2-4 on
page 34 shows the rear view of a 375 MHz POWER3 High Node packaging.
Table 2-1 375 MHz POWER3 SMP High Node
Node type
Feature code
Processor
Clock
Data/instruction L1 cache
L2 cache/processor
32
RS/6000 SP and Clustered IBM ^ pSeries Systems Handbook
375 MHz POWER3 SMP High Node
2058
64-bit POWER3-II
4-way, 8-way, 12-way, or 16-way
375 MHz
64 KB/32 KB
8 MB
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