Processor/L2 Cache Controller - IBM RS/6000 SP Handbook

system at any one time. The address bus includes status and coherency
response buses for returning flow control, error reports, or coherency information
for each request. It can support a new request every other bus cycle at a
sustained rate of over 40 million/sec.
The coherency protocol used is an enhanced Modified Exclusive Shared and
Invalid (MESI) protocol that allows for cache-to-cache transfers (intervention) on
both modified and shared data found in the L2 or L1 caches. The coherency and
data transfer burst size is 64 bytes. The bus was designed for glueless
attachment using latch-to-latch protocols and fully buffered devices. This enables
high system speeds, and the 332 MHZ SMP node can achieve a maximum data
rate of 1.3 GB/s when the data bursts are brick-walled (for example, four quad
words are transferred every 4 cycles).
The address, data, and tag buses are fully parity checked, and each memory or
cache request is range checked and positively acknowledged for error detection.
Any error will cause a machine check condition and be logged.

2.8.3 Processor/L2 cache controller

The 332 MHz SMP node X5 Level 2 (L2) cache controller incorporates several
technological advancements in design providing greater performance over
traditional cache designs. The cache controller is inline and totally contained in
one chip.
Integrated on the same silicon die as the controller itself are dual tag directories
and 256 KB of SRAM cache. The dual directories allow non-blocking access for
processor requests and system bus snoops. These directory arrays are fully
parity checked and, in the case of a parity error, the redundant array will be used.
The data arrays employ ECC checking and correction and a single bit error can
be detected and corrected with no increase in the cache latency. Multiple bit
ECC errors will cause a machine check condition. The cache is configured as an
8-way set-associative, dual sectored, 64 byte line cache. Internal design trade-off
performance studies have shown that for commercial workloads the miss rate is
comparable to a 1MB direct mapped L2 cache with 32 byte lines.
The L2 cache has two independent buses: One 60x bus connecting with the
PowerPC 604e microprocessor and one bus connecting to the SMP system bus.
The 60x bus (64 data bits) operates at the same speed as the processor core
(166 MHz) for a maximum data bandwidth of 1.2 GB/s. The L2 cache core logic
runs 1:1 with the processor clock as well and can source L2 data to the
processor in 5:1:1:1 processor clock cycles (5 for the critical double word, 1
additional clock for each additional double word). The SMP bus interface (128
data bits) operates at a 2:1 ratio (83 MHz) of the processor bus sustaining the 1.3
GB/s maximum data bandwidth.
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Chapter 2. SP internal processor nodes