Power3 Smp Node System Architecture; Power3 Microprocessor - IBM RS/6000 SP Handbook

2.6.1 POWER3 SMP node system architecture

POWER3 SMP node system design is based on the IBM PowerPC Architecture
and the RS/6000 Platform Architecture. The node is designed as a bus-based
symmetrical multiprocessor (SMP) system using a 64-bit address and a 128-bit
data system bus running at a 2:1 processor clock ratio. The memory-I/O
controller is a general purpose chip set that controls memory and I/O for
systems, such as the POWER3 SMP node, which implement the PowerPC MP
System bus (6xx bus). This chip set consists of two semi-custom CMOS chips,
one for address and control, and one for data flow. The memory-I/O controller
chip set includes an independent, separately-clocked mezzanine bus (6xx-MX
bus) to which three PCI bridge chips and the SP Switch MX2 Adapter are
attached. The POWER3 SMP system architecture partitions all the system logic
into the high speed processor-memory portion and to the lower speed I/O
portion. This design methodology removes electrical loading from the wide,
high-speed processor-memory bus (6xx bus) allowing this bus to run much
faster. The wide, high-speed 6xx bus reduces memory and intervention latency,
while the separate I/O bridge bus supports memory coherent I/O bridges on a
narrower, more cost-effective bus.

2.6.2 POWER3 microprocessor

The POWER3 design contains a superscalar core, which is comprised of eight
execution units, supported by a high bandwidth memory interface capable of
performing four floating-point operations per clock cycle. The POWER3 design
allows concurrent operation of fixed-point, load/store, branch, and floating-point
instructions. There is a 32 KB instruction and 64 KB data level 1 cache integrated
within a single chip in .25 um CMOS technology. Both instruction and data
caches are parity protected. The level 2 cache controller is integrated into the
POWER3 microprocessor with the data arrays and directory being implemented
with external SRAM modules. The POWER3 microprocessor has a dedicated
external interface (separate from 6xx bus interface) for the level 2 cache
accesses. Access to the 6xx bus and the level 2 cache can occur
simultaneously. The level 2 cache is a unified cache (that is, it holds both
instruction and data) and is configured for direct mapped configuration. The
external interface to the 4 MB of level 2 cache has 256-bit width and operates at
200 MHz. This interface is ECC protected. The POWER3 microprocessor is
designed to provide high performance floating-point computation. There are two
floating-point execution units, each supporting 3-cycle latency, 1-cycle
throughput, and double/single precision Multiply-Add execution rate. Hence, the
POWER3 microprocessor is capable of executing four floating-point operations
per clock cycle, which results in a peak throughput of 800 MFLOPS.
Chapter 2. SP internal processor nodes
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