375 Mhz Power3 Smp Nodes - IBM RS/6000 SP Handbook

375 MHz POWER3 SMP Thin Node (F/C 2056)
Current supported nodes (cannot be ordered anymore):
POWER3 SMP High Node (F/C 2054)
332 MHz SMP Wide Node (F/C 2051)
332 MHz SMP Thin Node (F/C 2050)
The previous nodes are referenced in Appendix B, "Hardware" on page 365.

2.2 375 MHz POWER3 SMP nodes

SP 375 MHz POWER3 SMP node system design is based on the IBM PowerPC
Architecture and the RS/6000 Platform Architecture. The node is designed as a
bus-based symmetrical multiprocessor (SMP) system, using a 64-bit address
and a 128-bit data system bus running (2048-bit for High Node) at a 4:1
processor/clock ratio. Attached to the system bus (6xx bus) are from 2 to16
POWER3-II (630+) microprocessors, and up to two memory subsystem.
The memory-I/O controller is a general purpose chip set that controls memory
and I/O for systems, such as the 375 MHz POWER3 SMP node, which
implement the PowerPC MP System bus (6xx bus). This chip set consists of two
semi-custom CMOS chips, one for address and control, and one for data flow.
The memory-I/O controller chip set includes an independent, separately-clocked
"mezzanine" bus (6xx-MX bus) to which PCI bridge chips and the SP Switch
MX2 Adapter are attached. The 375 MHz POWER3 SMP system architecture
partitions all the system logic into the high speed processor-memory portion and
to the lower speed I/O portion. This design methodology removes electrical
loading from the wide, high-speed processor-memory bus (6xx bus) allowing this
bus to run much faster. The wide, high-speed 6xx bus reduces memory and
intervention latency while the separate I/O bridge bus supports memory coherent
I/O bridges on a narrower, more cost-effective bus.
Figure 2-2 on page 29 shows the 375 MHz POWER3 SMP High Node
architecture.
Chapter 2. SP internal processor nodes
27