6Xx Bus; System Memory; I/O Subsystem - IBM RS/6000 SP Handbook

2.6.3 6xx bus

The 6xx bus or System bus, connects up to four processor cards to the
memory-I/O controller chip set. This bus is optimized for high performance and
multiprocessing applications. It provides 40 bits of real address and a separate
128-bit data bus. The address, data, and tag buses are fully parity checked, and
each memory or cache request is range checked and positively acknowledged
for error detection. Any error will cause a machine check condition and is logged
in AIX error logs. The 6xx bus runs at a 100 MHz clock rate, and peak data
throughput is 1.6 GB/second. Data and address buses operate independently in
true split transaction mode and are pipelined so that new requests may be issued
before previous requests are snooped or completed.

2.6.4 System memory

The SP POWER3 SMP system supports 256 MB to 16 GB of 10ns SDRAM.
System memory is controlled by the memory-I/O chip set via the memory bus.
The memory bus consists of a 128-bit data bus and operates at 100 MHz clock
cycle. This bus is separated from the System bus (6xx bus), which allows for
concurrent operations on these two buses. For example, cache to cache
transfers can occur while a DMA operation is in progress to an I/O device.
There are two memory cards slots in the system. Each memory card contains 16
DIMM slots. Only 128 MB memory DIMMs are supported. Memory DIMMs must
be plugged in pairs, and at least one memory card with minimum of 256 MB of
memory must be plugged in for system to be operational. System memory is
protected by Single Error Correction, Double Error Detection ECC code.

2.6.5 I/O subsystem

The I/O subsystem is similar to 375 MHz POWER3 describe in Section 2.2.3,
"I/O subsystem" on page 30. The System firmware and RTAS are similar to 375
MHz POWER3 describe in Section 2.2.5, "System firmware and RTAS" on
page 32.
Service Processor microcode and System firmware microcode are available in
the following Web site:
http://www.austin.ibm.com/support/micro/download.html
54 RS/6000 SP and Clustered IBM ^ pSeries Systems Handbook