Data Transceivers; Recovery And Bus Contention - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
When A5, A6 and A7 are high and ADS# is strobed, E2 on the decoder is enabled. Here, M/IO#
is low and D/C# is high, enabling inputs E1 and E3 of the decoder. When RDY# is active, E2 is
disabled and the address is no longer valid. Reset and timeout signals may also disable the address
decoding logic.
Because of its non-pipelined address bus, the basic I/O interface design for the Intel486 processor
does not require address latches following the decoder.
The number of decoders needed is usually a factor of memory mapping complexity.
7.2.5

Data Transceivers

Data transceivers are used for isolating the processor's data bus from the external data bus and
increasing the drive capability for larger fanouts. Transceivers are used to avoid the contention
on the data bus caused when slow devices perform a delayed read on the databus following a read
cycle. When a write cycle follows a read cycle, the Intel486 processor may drive the data bus be-
fore a slow device can remove its outputs from the bus, creating potential bus contention. If the
load on the Intel486 processor's data pins meets device specifications, and if the data float time
of the device is short enough, the transceivers can be omitted from the system.
There should be enough transceivers in the bus interface to accommodate the device with the
most inputs and outputs on the data bus. Only eight transceivers are needed if the widest device
has 16 data bits and if the I/O device addresses are connected only to the lower byte of the data
bus.
The 74S245 transceiver is controlled through two input signals:
•
Data Transmit/Receive (DT/R#)—The transceiver for write cycles is enabled when this
signal is high, and a read cycle is enabled when it is low. This signal is simply a latched
version of the Intel486 processor's W/R# output.
•
Data Enable (DEN#)—When low, this input enables the transceiver outputs. It is generated
by the byte swapping logic and by the BE3#–BE0# signals.
Data transceivers may be combined with byte swapping logic, depending upon whether a 32 bit
to 8/16/32-bit transfer is used. The implementation details of this logic are discussed in previous
sections.
7.2.6

Recovery and Bus Contention

Although data transceivers help to avoid data bus contention, I/O devices may still require a re-
covery period between back-to-back accesses. At higher Intel486 processor clock frequencies,
bus contention is more problematic, particularly because of the long float delay of I/O devices,
which can conflict with read data from other I/O devices or write data from the CPU. To ensure
proper operation, I/O devices require a recovery time between consecutive accesses. All slave de-
vices stop driving data on the bus on the rising edge of IOR#. After a delay which follows this
rising edge, the data bus floats.
When other devices drive data on to the bus before the data from the previous access floats, bus
contention occurs. The Intel486 processor has a fast cycle time (30 ns at 33 MHz), and the prob-
ability of bus contentions must be addressed.
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