Intel Embedded Intel486 Hardware Reference Manual page 214

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Signal
A31–A2
D31–D0
BE3#–BE0#
BS16#
LE/BE#
DP3–DP0
PCHK#
ADS#
W/R#
†
PORT#
RDY#
BRDY#
BLAST#
CLK
†
RESET
INT/INT#
BREQ
HOLD
HLDA
†
AHOLD
BOFF#
LOCK#
†
CA#
†
Signals marked with a dagger are not included on, or operate differently than, the Intel486™ processor
bus.
7-42
Table 7-12. 82596 Signals (Sheet 1 of 2)
Type
Address and Data Buses
O
I/O
O
I
I
I/O
O
Cycle Definition and Control
O
O
I
I
I
O
Bus Control
I
I
O
I
O
I
I
I
O
I
Description
Address
Data
Byte-enables
16-bit data bus size
Little endian or big endian byte ordering
Data parity
Parity error
Address status
Write or read
Port access
Non-burst data ready
Burst data ready
Last burst cycle
Clock
Reset
Interrupt
Bus request
Bus hold request
Bus hold acknowledgment
Address hold request
Bus backoff
Bus lock
Channel attention