Intel Embedded Intel486 Hardware Reference Manual page 204

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
TW
TW
TD
TD
TD
TD
†
T
T
Latches and data buffers can improve processor write performance. In
and data are both latched in a configuration called a posted write. Posted writes help increase sys-
tem performance by allowing the processor to complete a cycle without wait states. Once the data
and address are latched, RDY# can be asserted during the first T2 of an I/O write cycle. Thus, the
processor operation and the write cycle to the peripheral device can continue simultaneously.
This is illustrated in Figure
to RDY#) because the actual write overlaps other CPU bus cycles.
Address
Intel486™
Processor
7-32
Write Signal Valid Delay
VD
= T
VD PLDpd
= 10 ns
Write Data Valid Delay
VD
†
= T + T
VD VD BUFpd
= 19 + 9 = 28 ns
Write Data Float Time
FD
†
= T – T
FD FD BUFpd
= 0 + 9 = 9 ns
= T = Intel486™ processor write data valid delay (33 MHz)
VD 10
= T = Intel486 processor write data float delay (33 MHz)
FD 11
Figure 7-16. I/O Write Cycle Timing Analysis
7-18. The write cycle appears to be only two clocks long (from ADS#
I/O
Address
Latch
Data
Buffer
Data
Figure 7-17. Posted Write Circuit
Figure 7-17, I/O addresses
I/O
Address
Decode
I/O
Data
I/O Write
Latch
Data Bus
I/O
Device