Bus Functional Description - Intel Embedded Intel486 Hardware Reference Manual

BUS OPERATION
The arbitration logic may be implemented in several different ways. The first technique is to
"round-robin" or to "time slice" each master. Each master is given a block of time on the bus to
match their priority and need for the bus.
Another method of arbitration is to assign the bus to a master when the bus is needed. Assigning
the bus requires the arbitration logic to sample the BREQ or HOLD outputs from the potential
masters and to assign the bus to the requestor. A priority scheme must be included to handle cases
where more than one device is requesting the bus. The arbitration logic must assert HOLD to the
device that must relinquish the bus. Once HLDA is asserted by all of these devices, the arbitration
logic may assert HLDA or BACK# to the device requesting the bus. The requestor remains the
bus master until another device needs the bus.
These two arbitration techniques can be combined to create a more elaborate arbitration scheme
that is driven by a device that needs the bus but guarantees that every device gets time on the bus.
It is important that an arbitration scheme be selected to best fit the needs of each system's imple-
mentation.
The Intel486 processor asserts BREQ when it requires control of the bus. BREQ notifies the ar-
bitration logic that the processor has pending bus activity and requests the bus. When its HOLD
input is inactive and its HLDA signal is deasserted, the Intel486 processor can acquire the bus.
Otherwise if HOLD is asserted, then the Intel486 processor has to wait for HOLD to be deassert-
ed before acquiring the bus. If the Intel486 processor does not have the bus, then its address, data,
and status pins are 3-stated. However, the processor can execute instructions out of the internal
cache or instruction queue, and does not need control of the bus to remain active.
The address buses shown in Figure 4-8 and Figure 4-9 are bidirectional to allow cache invalida-
tions to the processors during memory writes on the bus.
4.3

BUS FUNCTIONAL DESCRIPTION

The Intel486 processor supports a wide variety of bus transfers to meet the needs of high perfor-
mance systems. Bus transfers can be single cycle or multiple cycle, burst or non-burst, cacheable
or non-cacheable, 8-, 16- or 32-bit, and pseudo-locked. Cache invalidation cycles and locked cy-
cles provide support for multiprocessor systems.
This section explains basic non-cacheable, non-burst single cycle transfers. It also details multi-
ple cycle transfers and introduces the burst mode. Cacheability is introduced in Section 4.3.3,
"Cacheable Cycles." The remaining sections describe locked, pseudo-locked, invalidate, bus
hold, and interrupt cycles.
Bus cycles and data cycles are discussed in this section. A bus cycle is at least two clocks long
and begins with ADS# asserted in the first clock and RDY# or BRDY# asserted in the last clock.
Data is transferred to or from the Intel486 processor during a data cycle. A bus cycle contains one
or more data cycles.
Refer to Section 4.3.13, "Bus States," for a description of the bus states shown in the timing dia-
grams.
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