Cascaded Interrupt Controllers - Intel Embedded Intel486 Hardware Reference Manual

7.5.2.2

Cascaded Interrupt Controllers

Figure 7-20 shows how several interrupt controllers can be cascaded to handle up to 64 interrupt
requests. One device acts as the master and the rest as slaves. The interface between these devices
resembles the single device interface with the following additional features:
•
The cascaded address outputs are used to provide address and chip select signals for the
slave controllers.
•
The interrupt request lines (IR7–IR0) of the master controller are connected to the INTR
outputs of the slave devices.
Programmable
Interrupt Controller
IRQ8
IRQ0
IRQ9
IRQ1
IRQ10
IRQ2
IRQ11
From ISA
IRQ3
Slots
IRQ12
IRQ4
IRQ13
IRQ5
IRQ14
IRQ6
IRQ15
IRQ7
The function of each slave controller is to identify the priorities among eight interrupt requests
and generate a single interrupt request for the master controller. The master controller must iden-
tify the priorities among eight slave controllers and transmit a single interrupt request to the
Intel486 processor.
Interrupt Controller
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Slave 82C59A
INTR
Cascade Bus
INTA#
Figure 7-20. Cascaded Interrupt Controller
PERIPHERAL SUBSYSTEM
Master 82C59A
Programmable
IRQ0
INTR
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
D7:D0
Bus Cycle
Type
Decoder
Intel486™ Processor
INTR
LOCK#
PLOCK#
M/IO#, D/C#, W/R#
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