Dynamic Data Bus Sizing - Intel Embedded Intel486 Hardware Reference Manual

The Intel486 processor includes bus control pins, BS16# and BS8#, which allow direct connec-
tion to 16- and 8-bit memories and I/O devices. Cycles of 32-, 16- and 8-bits may occur in any
sequence, since the BS8# and BS16# signals are sampled during each bus cycle.
The Ultra-Low Power Intel486 GX processor has a 16-bit external data bus.
All data transfers are done on the low order data bits (D15-D0) and parity is
generated and checked on pins DP0 and DP1. For this reason, dynamic data
bus sizing (using pins BS16# and BS8#) is not supported.
Memory and I/O spaces that are 32-bit wide are organized as arrays of four bytes each. Each four
bytes consists of four individually addressable bytes at consecutive byte addresses (see
Figure 4-2). The lowest addressed byte is associated with data signals D7–D0; the highest-ad-
dressed byte with D31–D24. Each 4 bytes begin at an address that is divisible by four.
Figure 4-2. Physical Memory and I/O Space Organization
16-bit memories are organized as arrays of two bytes each. Each two bytes begins at addresses
divisible by two. The byte enables BE3#–BE0#, must be decoded to A1, BLE# and BHE# to ad-
dress 16-bit memories.
To address 8-bit memories, the two low order address bits A0 and A1 must be decoded from
BE3#–BE0#. The same logic can be used for 8- and 16-bit memories, because the decoding logic
for BLE# and A0 are the same. (See
ries.")
4.1.2

Dynamic Data Bus Sizing

Dynamic data bus sizing is a feature that allows processor connection to 32-, 16- or 8-bit buses
for memory or I/O. The Intel486 processors can connect to all three bus sizes, except for the Ul-
tra-Low Power Intel486 GX processor, uses a 16-bit data bus. Transfers to or from 32-, 16- or 8-
bit devices are supported by dynamically determining the bus width during each bus cycle. Ad-
dress decoding circuitry may assert BS16# for 16-bit devices or BS8# for 8-bit devices during
NOTE
32-Bit Wide Organization
FFFFFFFFH
00000003H
BE3#
BE2# BE1#
16-Bit Wide Organization
FFFFFFFFH
00000001H
BHE# BLE#
Section 4.1.3, "Interfacing with 8-, 16-, and 32-Bit Memo-
FFFFFFFCH
00000000H
BE0#
FFFFFFFEH
00000000H
BUS OPERATION
4-3