Intel Embedded Intel486 Hardware Reference Manual page 250

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
A31–A30,
A26–A2
SRESET/INIT
HD31–HD0
HDP3–HDP0
BE3#–BE0#
M/IO#
D/C#
W/R#
PCD/CACHE#
ADS#
RDY#
BRDY#
BLAST#
HOLD
HLDA
AHOLD
EADS#
KEN#
HITM#
SMI#
SMIACT#
CI3E
CI302
CWE1#–CWE0#
COE1#–COE0#
TWE#
TAG8–TAG0
PCLKIN
HCLKIN
CLK2IN
CPURST
KBDRST#
The ISA bridge links the ISA bus and Host bus, and integrates the common I/O functions found
in today's ISA-based systems: a seven channel DMA controller, two 82C59 interrupt controllers,
an 8254 timer/counter, Intel SMM power management support, and control logic for NMI gen-
eration. The ISA bridge also provides the decode for the external BIOS, real time clock, and key-
8-22
Host
CPU
Interface
SMM
Interface
Cache
Interface
Clocks
and
Reset
Figure 8-6. System Controller Block Diagram
PCI Bus
Interface
MUX
IDE
Interface
System
controller/
ISA bridge
Interface
PCI
Arbitration
and
Host Bus
Slave
Device
DRAM
Interface
FRAME#
TRDY#
IRDY#
LOCK#
STOP#
PAR
SERR#
DEVSEL#
C/BE3#–C/BE0#
AD22–AD16
AD31 or IDE1CS#
AD30 or IDE3CS#
AD29 or DIR
AD28 or IORDY
AD27–AD25 or
IDEA2–IDEA0
AD24 or IOR#
AD23 or IOW#
AD15–AD0 or
IDED15–IDED0
LBIDE#
CMDV#
SIDLE#
LREQ#
LGNT#
PREQ1#/HDEV#
PREQ0#
PGNT1#/HRDY#
PGNT0#
MA10–MA0
RAS4#–RAS0#
CAS7#–CAS0#
WE#