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Users sometimes adopt a buffered write-through approach in which the write accesses to the main
memory can be buffered with a N-deep pipeline. A number of words are stored in pipelined reg-
isters, and will subsequently be written to the main memory. The processor can begin a new op-
eration before the write operation to main memory is completed. If a read access follows a write
access, and a cache hit occurs, then data can be accessed from the cache memory while the main
memory is updated. When the N-deep pipeline is full, the processor must wait if another write
access occurs and the main memory has not yet been updated. A write access followed by a read
miss also requires the processor to wait because the main memory has to be updated before the
next read access.
Pipeline configurations must account for multiprocessor complications when another processor
accesses a shared main memory location which has not been updated by the pipeline. This means
the main memory hasn't been updated, and the memory controller must take the appropriate ac-
tion to prevent data inconsistencies.
6.4.2
Write-Back System
In a write-back system, the processor writes data into the cache and sets a "dirty bit" which indi-
cates that a word had been written into the cache but not into the main memory. The cache data
is written into the main memory at a later time and the dirty bit is cleared. Before overwriting any
word or block in the cache, the cache controller looks for a dirty bit and updates the main memory
before loading the cache with the new data.
A write-back cache accesses memory less often than a write-through cache because the number
of times that the main memory must be updated with altered cache locations is usually lower than
the number of write accesses. This results in reduced traffic on the main memory bus.
A write-back cache can offer higher performance than a write-through cache if writes to main
memory are slow. The primary use of the a write-back cache is in a multiprocessing environment.
Since many processors must share the main memory, a write-back cache may be required to limit
each processor's bus activity, and thus reduce accesses to main memory. It has been shown that
in a single-CPU environment with up to four clock memory writes, there is no significant perfor-
mance difference between a write-through and write-back cache.
There are some disadvantages to a write-back system. The cache control logic is more complex
because addresses have to be reconstructed from the tag RAM and the main memory has to be
updated along with the pending request. For DMA and multiprocessor operations, all locations
with an asserted dirty bit must be written to the main memory before another device can access
the corresponding main memory locations.
6.4.3
Cache Consistency
Write-through and write-back systems require mechanisms to eliminate the problem of stale main
memory in a multiprocessing system or in a system with a DMA controller. If the main memory
is updated by one processor, the cache data maintained by another processor may contain stale
data. A system that prevents the stale data problem is said to maintain cache consistency. There
are four methods commonly used to maintain cache consistency: snooping (or bus watching),
broadcasting (or hardware transparency), non-cacheable memory designation, and cache flush-
ing.
CACHE SUBSYSTEM
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