Intel Embedded Intel486 Hardware Reference Manual page 279

chance for hiding the precharge time is increased. As a result, the performance increases with ad-
ditional banks.
Figure 9-6 demonstrates the performance differences between an interleaved system supporting
one clock bursting and a non-interleaved system in two applications. The performance levels are
measured with respect to a zero wait state (2-1-2 bus). Interleaving can improve system perfor-
mance as much as 15%.
100
90
80
70
60
Figure 9-6. Performance in Interleaved and Non-Interleaved Systems
9.8.2 Impact of Performance for Posted Write Cycles
In an Intel486 processor system, the on-board cache reduces the external read cycles so that as
much as 77 percent of the external bus cycles are write cycles. In program execution, writes occur
in strings of two about 60 to 70% of the time. Writes occur in strings of three 40-50% of the time.
The DRAM subsystem must be optimized for write strings; one method is to support posted
writes with write buffers. Posting writes means that RDY# is returned to the CPU before the write
transaction is completed. This avoids the CPU depending on the write latency time. This is dis-
cussed further in Chapter 5, "Memory Subsystem Design." Figure 9-6
mance in two different applications and shows the improvement gained by using posted writes.
Intel486™ CPU Performance vs. Interleaving
Application A
Interleaved
Application A
Non-Interleaved
PERFORMANCE CONSIDERATIONS
Application B
Interleaved
Application B
Non-Interleaved
demonstrates the perfor-
9-15