Intel Embedded Intel486 Hardware Reference Manual page 261

SYSTEM BUS DESIGN
Memory Chip Select, 16 MEMCS16#, is driven low by ISA slaves that are 16-bit memory devic-
es. MEMCS16# is an input when the ISA bridge owns the ISA bus. MEMCS16# is an output
when an ISA bus master owns the ISA bus. The ISA bridge drives this signal low during ISA
master to main memory cycles.
Memory Read, MEMR#, is the command to a memory slave that it may drive data onto the ISA
data bus. MEMR# is an output when the ISA bridge is a master on the ISA bus and an input when
an ISA master, other then the ISA bridge, owns the ISA bus. This signal is also driven by the ISA
bridge during refresh cycles. For DMA cycles, the ISA bridge, as a master, asserts MEMR#. This
signal is 3-stated after a hard reset.
Memory Write, MEMW#, is the command to a memory slave that it may latch data from the ISA
data bus. MEMW# is an output when the ISA bridge owns the ISA bus and an input when an ISA
master, other then the ISA bridge, owns the ISA bus. For DMA cycles, the ISA bridge, as a mas-
ter, asserts MEMW#. This signal is 3-stated after a hard reset.
Standard Memory Read, SMEMR#, is asserted to request an ISA memory slave to drive data onto
the data lines. If the access is below the 1 Mbyte range (00000000-000FFFFFh) during DMA
compatible, ISA bridge master, or ISA master cycles, the ISA bridge asserts SMEMR#.
SMEMR# is a delayed version of MEMR#. This signal is deasserted after a hard reset.
Standard Memory Write, SMEMW#, is asserted to request an ISA memory slave to accept data
from the data lines. If the access is below the 1 Mbyte range (00000000-000FFFFFh) during
DMA compatible, ISA bridge master, or ISA master cycles, the ISA bridge asserts SMEMW#.
SMEMW# is a delayed version of MEMW#. This signal is deasserted after a hard reset.
Zero Wait-States, ZEROWS#, is asserted by an ISA slave after its address and command signals
have been decoded to indicate that the current cycle can be shortened. If IOCHRDY is deasserted
and ZEROWS# is asserted during the same clock, then ZEROWS# is ignored and wait-sates are
added as a function of IOCHRDY (i.e. IOCHRDY has precedence over ZEROWS#).
System Data, SD15–SD8, provide the 16-bit data path for devices residing on the ISA bus. SD15–
SD8 correspond to the high order byte and SD7–SD0 correspond to the low order byte. SD15–
SD0 are undefined during refresh. These signals are 3-stated after hard reset.
8.4.6 DMA Controller
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven in-
dependently programmable channels (Channels 3–0 and Channels 7–5). The DMA supports
8/16-bit devices using ISA-compatible timings and 27-bit addressing as an extension of the ISA-
compatible specification. The DMA channels can be programmed for either fixed (default) or ro-
tating priority. The DMA controller also generates ISA refresh cycles. DMA Channel 4 is used
to cascade the two controllers and default to cascade mode in the DMA Channel Mode (DCM)
register (Figure 10). In addition to accepting requests from DMA slaves, the DMA controller also
responds to requests that are initiated by software. Software may initiate a DMA service request
by setting any bit in the DMA Channel Request register to a 1. The DMA controller for Channels
3–0 is referred to as "DMA-1" and the controller for Channels 7–4 is referred to as "DMA-2".
Each DMA channel is hardwired to the compatible settings for DMA device size channels 3–0
are hardwired to 8-bit, count-by-bytes transfers and channels 7–5 are hardwired to 16-bit, count-
by-words (address shifted) transfers. The ISA bridge provides the timing control and data size
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