Non-Cacheable Non-Burst Single Cycle; No Wait States - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4.3.1

Non-Cacheable Non-Burst Single Cycle

4.3.1.1

No Wait States

The fastest non-burst bus cycle that the Intel486 processor supports is two clocks. These cycles
are called 2-2 cycles because reads and writes take two cycles each. The first "2" refers to reads
and the second "2" to writes. If a wait state needs to be added to the write, the cycle is called "2-
3."
Basic two-clock read and write cycles are shown in
a cycle by asserting the address status signal (ADS#) at the rising edge of the first clock. The
ADS# output indicates that a valid bus cycle definition and address is available on the cycle def-
inition lines and address bus.
Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
DATA
PCHK#
†
To Processor
‡
From Processor
The non-burst ready input (RDY#) is asserted by the external system in the second clock. RDY#
indicates that the external system has presented valid data on the data pins in response to a read
or the external system has accepted data in response to a write.
The Intel486 processor samples RDY# at the end of the second clock. The cycle is complete if
RDY# is asserted (LOW) when sampled. Note that RDY# is ignored at the end of the first clock
of the bus cycle.
The burst last signal (BLAST#) is asserted (LOW) by the Intel486 processor during the second
clock of the first cycle in all bus transfers illustrated in
4-16
T1 T2 T1
†
Read Write
Figure 4-10. Basic 2-2 Bus Cycle
Figure 4-10. The Intel486 processor initiates
T2 T1 T2
‡ †
Read
Figure 4-10. This indicates that each trans-
T1 T2 Ti
‡
Write
242202-031