Intel Embedded Intel486 Hardware Reference Manual page 236

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
IRQ <1,3-7, 8#,
9-15>
INT
BCLK
NMI
IOCHK#
PARITY#
Figure 8-3. Block Diagram of Integrated System Peripheral (ISP)
The EISA bus buffers (EBB) are used to interconnect the host data and address buses to the EI-
SA/ISA data and address bus. The EBB integrates multiple address or data latches and buffers
that are typically used in EISA systems, and operates in various modes to support data and ad-
dress interfaces. It has a 32-bit mode without parity and a 32-bit data mode with parity support
8-8
Bus Interface
15 Level
Interrupt
Control
IRQ0
CLK
NMI
Logic
Timer 1/Counter 0
Timer 1/Counter 1
Timer 1/Counter 2
Timer 2/Counter 0
Timer 2/Counter 2
SPKR SLOWH#
DMA
Controller
and
Refresh
Generator
System
Arbiter
Logic
OSC
EOP
GT16M#
RST
AEN#
DREQ
DACK#
MREQ#
MACK#
REFRESH#
DHLDA
CPUMISS#
DHOLD
EMSTR16#
EXMASTER#