Intel Embedded Intel486 Hardware Reference Manual page 208

Embedded intel486 processor

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL

Figure 7-19. Intel486™ Processor Interface to the 82C59A

An interrupt activates the Interrupt output of the 82C59A, which is connected to the INTR input

(interrupt request) of the Intel486 processor. The processor automatically performs two consec-

utive interrupt acknowledge cycles. The 82C59A device's timings are as follows:

Each interrupt acknowledge cycle must be extended by at least one wait state, which is

implemented by the wait state generator logic described in

Four idle cycles must be inserted between two interrupt acknowledge cycles.

Transceivers

Section 7.2, "Basic Peripheral

Chapters

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