Processor; Secondary Cache - NEC POWERMATE 4100M Service Manual

Processor

The PowerMate systems use the following processors.
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PowerMate 433D – uses the 486SX with a 33 MHz clock speed
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PowerMate 466D and 466M – use the 486DX2 with a 66-MHz internal clock
speed and a 33-MHz external clock speed.
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PowerMate 4100M – use the 486DX4 with a 100-MHz internal clock speed and a
33-MHz external clock speed.
The processors are advanced 32-bit processors designed to optimize multitasking operating
systems. The 32-bit registers and data paths support 32-bit addresses and data types.
The processor is installed in a 237-pin, zero-insertion-force (ZIF) processor socket. This
socket allows the installation of the 486SX, DX2 and DX4 processors and the next genera-
tion of Intel OverDrive processors based on the Pentium core (PGA type package). When
upgrading processors they must operate with and external clock of 25 or 33 MHz.
The 486DX2 is exactly like previous 486DXs except that it runs twice as fast internally.
When the interface bus portion of the DX2 accesses main memory, executes I/O instruc-
tions, or accesses one of the other chips on the system board, the DX2 operates at 33 MHz.
The DX2 works at 66 MHz when accessing its internal registers, refers to a memory loca-
tion alPowerMate mapped into its internal cache, or performs a floating-point operation and
CPU operations.
The DX4 runs three times as fast internally. When the interface portion accesses external
registers it operates at 33 MHz and works at 100 MHz when accessing its internal registers.

Secondary Cache

The 8-KB primary cache (16-KB of primary cache in the DX4) is integrated into the proc-
essor. The system board provides an 80-pin SIMM socket for an optional 256 KB of sec-
ondary cache, external to the processor. Cache memory improves read performance by
holding copies of code and data that are frequently requested from the system memory by
the processor. Cache memory is not considered part of the possible 128 MB of total mem-
ory capacity.
The cache is connected directly to the processor address bus and uses physical addresses. A
bus feature known as burst enables fast cache fills. Memory areas (pages) can be designated
as cacheable or non-cacheable by software. The cache can also be enabled and disabled by
software.
The write strategy of the cache (primary and secondary) is write-through. If the write is a
cache hit, an external bus cycle is generated and information is written to the cache. Any
area of memory can be cached in the system. Non-cacheable portions of memory are de-
fined by software. The cache can be cleared by software instructions.
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