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PC Card Logic
SDRAM
NAND Flash
Secure Digital Card Interface
Serial EEPROM
Revision E
Equipment Overview: Theory of Operation
transistor driver Q100. Full volume is achieved by driving the fundamental beep
tone directly to the speaker. Half volume is achieved by gating the speaker signal
with a 48KHz square wave, reducing the amplitude by 50%. The LS1 is also used by
the communication board for modem sound. The modem speaker signal from the
module is amplified and driven though Q101.
The -006 and -007 board is designed to support multiple products and one of the
requirement during the design phase was the support for PC Card, through a
daughter board. But this requirement was removed later on. The PC Card logic use
the two ATMEL chip select signals and bus control signals to generate, IO, Memory
and Attribute memory access to PC Card. The PC Card bus controls signals from
FPGA and the address and data lines form ATMEL are buffered and terminated to
daughter board interface connector J21.
Program code and working data is stored in a four 4MWord bank of 32-bit wide
memory (64Mbytes). This memory is made up of two 256 Mbit SDRAMs each 16
bits wide. All bus timing and refresh control is performed by the ATMEL CPU
SDRAM controller. The SDRAM clock rate is one third of the ATMEL CPU clock
or 59.904 Mhz. Though the size requirement is less, the video frame buffer also use
256Mbit SDRAM.
There are two 32 Mbytes NAND Flash in -006 and -007 boards. One is used for
storing FPGA configuration data and system software. The other is for data storage.
The access to NAND flash is through a dedicated smart media interface logic
provided by ATMEL CPU. Unlike the -005 board, NAND flash chips are accessed
through the buffer U55 instead of Xbus. The NAND Flash control signals are
changed to GPIO mode while configuring FPGA in fly by fashion. Wear-leveling
algorithm is implemented for the data storage NAND flash to extend the life.
The SD card interface is provided to support software update and external data
storage application. The socket provide card detection and write protect status
signal. ATMEL CPU has built in secure digital card interface controller. But there is
a bug in the current revision of the ATMEL CPU, which swaps bits within the
transmitted / received nibbles. Since the software overhead to correct this is high,
SD card interface support only SPI mode. However all the SD card interface signals
are terminated at the connector through a set of resistors, which are not placed, so
that we can go for the true SD card interface in future.
System setup information, option enables and other machine specific data is stored
in 32 KByte serial EEPROM. The SPI interface to the EEPROM is provided by the
FPGA.
MAC 5500 resting ECG analysis system
2020299-020
2-25
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