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BBus Interface
PWM Analog Outputs
Beep Generator
2-24
Equipment Overview: Theory of Operation
that no interrupt support is required. The ATMEL CPU polls a ready bit to
determine when the transfer is complete.
There are several I/O functions poorly suited to direct control by the ATEML CPU,
whether for reasons of software complexity or power consumption. These I/O
functions are provided by three 68HC705 microcontrollers placed strategically
around the board (Moe, Larry and Shemp). Each of these three microcontrollers
must communicate with the ATMEL CPU. BBus is a simple 1-wire point-to-point
interface designed specifically for this purpose. The FPGA provides a single BBus
transceiver and a 3-way bidirectional multiplexer to attach the three BBus
microcontrollers. For more Bbus information see the microcontroller firmware
source files. From the programmer's standpoint, BBus operates like SPI, where each
transaction exchanges a single byte between the host and peripheral.
Four PWM channels are provided for the generation of analog outputs. Three of the
outputs are available on the Analog I/O connector; the fourth is available internally
for future use (if any). One of the PWM channels provides 12-bit resolution at 6KHz
cycle rate; the other three provide 8-bit resolution at 96KHz cycle rate. The ATMEL
CPU simply writes the desired value into a PWM data register and the output duty
cycle changes on the next PWM cycle. External analog circuitry converts the PWM
logic signals to smooth analog voltages. The 12-bit PWM channel is intended for
ECG output and produces a swing of +10 to -10V. The two 8-bit channels provide a
unipolar 10V output. Regardless of the resolution or swing range of each PWM
channel, the FPGA treats the data value as a signed 16-bit number representing a
voltage from +10V (0x7fff) to -10V(0x8000). Logic in each PWM channel ensures
that the closest possible voltage is generated for each data value (ex. 0x8000 on an
8-bit channel produces zero volts output).
The FPGA PWM output signals contain a substantial amount of noise from +3V-M
supply fluctuations. To reduce noise and establish an accurate reference level, the
PWM signals are buffered by CMOS inverters (U20) that are powered from
REF2V5. Although the CMOS inverters are powered by 2.5 Volts but are driven by
3.3 Volt logic, no problem exists as this is allowed with VHC logic. The PWM
output signals are then low pass filtered (R186,C186, etc) before being passed to the
output amplifiers. The ECG output channel amplifier injects an offset current
derived from REF2V5 to achieve bipolar operation. The DC outputs operate in
unipolar fashion, eliminating the vexing MAX-1 offset problems. No zero
calibration is required for the DC outputs. Since the ECG output is an AC signal, no
offset adjust is required there either.
The output amplifiers provide additional low pass filtering (R178,C178, etc.). ESD
protection and additional PWM carrier filtering is provided by 0.1µF filter
capacitors. To prevent amplifier oscillation, blocking resistors are placed between
the amplifier outputs and the filter capacitors.
A simple tone generator with two volume levels provides system beeps and key
clicks. Frequencies of 250Hz, 500Hz and 1KHz are provided at both low and high
volume. The logic level output signal drives LS1 through an open collector
MAC 5500 resting ECG analysis system
2020299-020
Revision E
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