GE MAC 5500 Service Manual page 26

2-8
Equipment Overview: Theory of Operation

External Bus Interface (EBI)
- Supports SDRAM, Static Memory, Burst Flash, Glueless Connection
to CompactFlash®, SmartMedia
 System Peripherals for Enhanced Performance:
- Enhanced Clock Generator and Power Management Controller
- Two On-chip Oscillators with Two PLLs
- Very Slow Clock Operating Mode and Software Power Optimization
Capabilities
- Four Programmable External Clock Signals
- System Timer Including Periodic Interrupt, Watchdog and Second
Counter
- Real-time Clock with Alarm Interrupt
- Debug Unit, Two-wire UART and Support for Debug Communication
Channel
- Advanced Interrupt Controller with 8-level Priority, Individually
Maskable Vectored Interrupt Sources, Spurious Interrupt Protected
- Seven External Interrupt Sources and One Fast Interrupt Source
- Four 32-bit PIO Controllers with Up to 122 Programmable I/O
Lines, Input Change Interrupt and Open-drain Capability on Each Line
- 20-channel Peripheral Data Controller (DMA)

Multimedia Card Interface (MCI)
- Automatic Protocol Control and Fast Automatic Data Transfers
- MMC and SD Memory Card-compliant, Supports Up to Two SD
Memory Cards
 Three Synchronous Serial Controllers (SSC)
- Independent Clock and Frame Sync Signals for Each Receiver and
Transmitter
- I 2 S Analog Interface Support, Time Division Multiplex Support
- High-speed Continuous Data Stream Capabilities with 32-bit Data
Transfer
 Four Universal Synchronous/Asynchronous Receiver/Transmitters
(USART)
- Support for ISO7816 T0/T1 Smart Card
- Hardware and Software Handshaking
- RS485 Support, IrDA Up To 115 Kbps
- Full Modem Control Lines on USART1
 Master/Slave Serial Peripheral Interface (SPI)
- 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip
Selects
 Two 3-channel, 16-bit Timer/Counters (TC)
- Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
- Double PWM Generation, Capture/Waveform Mode, Up/Down
Capability
MAC 5500 resting ECG analysis system
2020299-020

and NAND Flash
Revision E