GE LPS-O Instruction Manual page 267

13 XPRESSION BUILDER
13.2 DESIGN CONSIDERATIONS
Xpression Builder logic is processed every other millisecond. This should be considered when designing logic
to implement in the relay. The more gates that are connected in series, the longer the time delay from the initial
logic input to the final logic output (roughly 2 ms per gate) of the expected result. This delay applies to the
Xpression Builder logic only. The scheme logic outputs of the relay will not be delayed with the use of config-
urable logic.
For example, the TRIP (flag #33) output of the scheme logic when directly connected to an output contact will
close that contact when it becomes high (logic 1) with no additional processing delay as shown in Figure 13–4:
LOGIC PROCESSING DELAY part A. If the TRIP flag is first connected to a Boolean gate before it reaches an
output contact, a gate processing delay of 2 ms should be added to the expected function operating time as
shown in Figure 13–4: LOGIC PROCESSING DELAY part B. This should be taken into consideration in the
design of the relay configurable logic. This is why it is recommended all user defined logic be tested in a labo-
ratory environment before installation in the field. This will ensure user confidence and expected performance
of the configurable logic developed with the relay internal flags.
a) BOOLEAN OPERATORS
The operation of the Boolean operators (AND, OR, and NOT) are self explanatory. Each gate may have up to
four (4) inputs. Each of the inputs may be logically inverted by clicking the right mouse button when the cursor
is at the input of the gate. A small circle at the gate input will indicate the inversion of the input signal. The out-
put can also be inverted by clicking the right mouse button when the cursor is at the output of the gate. A small
circle at the gate output will indicate the inversion of the output signal.
b) LATCHES
A "D" flip-flop is used in the Xpression Builder logic as shown in Figure 13–5: LATCH AND TRUTH TABLE. The
D input is where the data bit to be stored is applied. The T or clock input controls the flip-flop. It determines
whether the data on the D input line is recognized (clocked) or ignored. If the T input line is high (binary 1), the
GE Power Management
Trip
(A)
Trip
(B)
input always low
(logic 0)
T
r
i
p
T
1
(A)
PU ~ 2 ms
DO ~ 2 ms
Figure 13–4: LOGIC PROCESSING DELAY
13.2.2 BOOLEAN OPERATORS, LATCHES, TIMERS, & COUNTERS
LPS-O Line Protection System
13.2 DESIGN CONSIDERATIONS
T1
T1
T
r
i
p
DO
PU
T
1
(B)
13.2.1 OVERVIEW
13
13-
5