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U0TSR — UART0 Test Register
U1TSR — UART1 Test Register
15
14
13
12
R
0
0
FRC
LOOP
W
PERR
RESET:
0
0
0
0
FRC PERR — Force Parity Error
When set, this bit forces the transmitter to generate a parity error if parity is enabled.
This bit is provided for system debugging.
0 = Generate normal parity
1 = Generate inverted parity (error)
At reset, this bit is cleared to zero.
LOOP — Loop TX and RX for Test
This bit controls loopback for test purposes. When this bit is high, the receiver input is
internally connected to the transmitter and ignores the RxD pin. The transmitter is
unaffected by this bit. This loopback operates to connect the data on the TxD pin
directly to the voting logic. If infrared mode is enabled (IR_EN is active), the effect of
activating this bit is to put an IR-formatted bit stream into the voting logic, which will
yield odd results. Do not use this loopback if IR_EN is active.
0 = Normal receiver operation
1 = Internal connect transmitter output to receiver input
At reset, this bit is cleared to zero.
LOOP IR — Loop TX and RX for IR Test
This bit controls a loopback from transmitter to receiver in the infrared interface.
0 = No IR loop
1 = Connect IR transmit to IR receiver
At reset, this bit is cleared to zero.
C.9.8 UART Port Control Register (UPCR)
The read/write UART port control register controls the functionality of UART GPIO
pins.
U0PCR — UART0 Port Control Register
U1PCR — UART1 Port Control Register
15
14
13
12
R
0
0
0
W
RESET:
MOTOROLA
C-44
Freescale Semiconductor, Inc.
11
10
9
0
LOOP
0
IR
0
0
0
Figure C-42 UART Test Register
11
10
9
0
0
0
0
Figure C-43 UART Port Control Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
8
7
6
5
0
0
0
0
0
0
0
0
8
7
6
5
0
0
0
0
10009088
1000A088
4
3
2
1
0
0
0
0
0
0
0
0
1000908A
1000A08A
4
3
2
1
0
PC3
PC2
PC1
PC0
0
0
0
MMC2001
REFERENCE MANUAL
0
0
0
0
0
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