Fast Interrupt Enable Register (Fier; Normal Interrupt Enable Register; Fast Interrupt Enable Register - Motorola M-CORE MMC2001 Series Reference Manual

NIER — Normal Interrupt Enable Register
31 30 29 28
EN31 EN30 EN29 EN28
RESET:
0 0 0 0
15 14 13 12
EN15 EN14 EN13 EN12
RESET:
0 0 0 0
Figure C-2 Normal Interrupt Enable Register
ENx — Enable Normal Interrupt Flag x
This bit enables the corresponding interrupt source to request a normal interrupt.
0 = Disable
1 = Enable
A reset operation clears this bit.
When the enable flag is set and the corresponding interrupt line is asserted, the inter-
rupt controller asserts a normal interrupt request. Enabling an interrupt source which
has an asserted request causes that interrupt to become pending, and a request to
the CPU is asserted if not already outstanding.
C.2.3 Fast Interrupt Enable Register (FIER)
Access the 32-bit fast interrupt enable register with 32-bit loads and stores only.
FIER — Fast Interrupt Enable Register
31 30 29 28
EF31 EF30 EF29 EF28
RESET:
0 0 0 0
15 14 13 12
EF15 EF14 EF13 EF12
RESET:
0 0 0 0
EFx — Enable Fast Interrupt Flag x
This bit enables the corresponding interrupt source to request a fast interrupt.
0 = Disable
1 = Enable
A reset operation clears this bit.
MMC2001
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27 26 25 24
EN27 EN26 EN25 EN24
0 0 0 0
11 10 9 8
EN11 EN10 EN9 EN8
0 0 0 0
27 26 25 24
EF27 EF26 EF25 EF24
0 0 0 0
11 10 9 8
EF11 EF10 EF9 EF8
0 0 0 0
Figure C-3 Fast Interrupt Enable Register
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23 22 21 20
EN23 EN22 EN21 EN20
0 0 0 0
7 6 5 4
EN7 EN6 EN5 EN4
0 0 0 0
23 22 21 20
EF23 EF22 EF21 EF20
0 0 0 0
7 6 5 4
EF7 EF6 EF5 EF4
0 0 0 0
10000004
19 18 17 16
EN19 EN18 EN17 EN16
0 0 0 0
3 2 1 0
EN3 EN2 EN1 EN0
0 0 0 0
10000008
19 18 17 16
EF19 EF18 EF17 EF16
0 0 0 0
3 2 1 0
EF3 EF2 EF1 EF0
0 0 0 0
MOTOROLA
C-3