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MB0
(byte addr
0,4,8,C,...)
MB1
(byte addr
1,5,9,D,...)
MEMORY
PORT
MB2
(byte addr
2,6,A,E,...)
MB3
(byte addr
3,7,B,F,...)
Connection Cases
Figure 2-6 External Multiplexer Connections
Table 2-3 lists the combinations of the TSIZx, ADDR1, and ADDR0 signals that are
used for each possible transfer size and alignment. In Table 2-3, MB0–MB3 indicate
the portion of the requested operand that is read or written during that bus transfer.
For word transfers, all bytes are valid as listed and correspond to portions of the
requested operand. The bytes labeled with a dash are not required; they are ignored
on read transfers and driven with undefined data on write transfers.
2.8.5 Processor Instruction/Data Transfers
The transfer of data between the processor and other devices involves the address
bus, data bus, transfer attributes, and control signals. The address and data buses
are parallel, non-multiplexed buses that support aligned byte, halfword, and word
transfers. All bus input and output signals are sampled or driven with respect to one of
the edges of the CLK signal. The M•CORE moves data on the bus by issuing control
signals and using a handshake protocol to ensure correct data movement.
Access requests are generated in an overlapped fashion in order to support sus-
tained single-cycle transfers. Once an access has been accepted, the processor is
free to change the current request. Access information must therefore be latched by a
slave device.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
f, g
d, f, g
Multiplexer
Structure
INTEGER CPU
For More Information On This Product,
Go to: www.freescale.com
g
g
DATA[31:24]
DATA[23:16]
M•CORE
DATA[15:8]
DATA[7:0]
MOTOROLA
2-13
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