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OVW — Counter Overwrite Enable
This bit controls what happens to the counter value when the modulus latch is written.
0 = Modulus latch is a holding register for values to be loaded into the counter
when the count expires to zero.
1 = Modulus latch is transparent. All writes to the latch will also overwrite the
counter contents
ITIE — PIT Interrupt Enable
This bit controls the PIT interrupt function.
0 = ITIF is inhibited from reaching the CPU
1 = ITIF is allowed to request an interrupt
ITIF — PIT Interrupt Flag
This bit is the PIT interrupt flag. It is cleared by writing a one to this bit or by writing to
the PIT data register.
0 = No PIT interrupt present.
1 = PIT interrupt is present.
RLD — Counter Reload Control
This bit controls whether the value contained in the modulus latch is reloaded into the
counter when the counter reaches a count of zero or whether the counter rolls over
from 0 to 0xFFFF.
0 = Counter rolls over to 0xFFFF.
1 = Counter is reloaded from the modulus latch.
EN — PIT Enable
This bit controls the PIT enable function.
0 = PIT is disabled
1 = PIT is enabled
C.3.10 PIT Data Register (ITDR)
On a write, the data becomes the new timer modulus. This value is retained and is
used at the next and all subsequent reloads until changed by another write to ITDR.
This value is initialized to the maximum count of 0xFFFF on reset. On a read, the
ITDR returns the value written in the modulus latch. The only way to directly change
the value of the count is to preload a modulus with the OVW bit set to one. The
counter value can be read from the PIT alternate data register.
Access this register with 32-bit loads and stores only.
MOTOROLA
C-12
Freescale Semiconductor, Inc.
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
MMC2001
REFERENCE MANUAL
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