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9.5.7 Watchdog Timer in Debug Mode
In debug mode, the watchdog may either continue to run or be halted. If the WDBG
(watchdog debug enable) bit is set in the watchdog control register (WCR), the watch-
dog is halted. At this point, the timer is stopped, but register read and write accesses
function normally. In this mode, the WCR one-time-write lock is disabled and the con-
trol bits can be updated.
If the WCR is updated in debug mode, it will remain updated when
debug mode is exited.
9.5.8 Watchdog Timer Programming Model
The watchdog programming model consists of a control register and a service regis-
ter.
9.5.8.1 Watchdog Control Register (WCR)
This register contains fields that control the operation of the watchdog in different
modes of operation. The write-once bits can only be written once after a reset condi-
tion. Subsequent attempts to write to them will not affect the data previously written.
Access this register with 32-bit loads and stores only.
WCR — Watchdog Control Register
31
30
29
28
R
0
0
0
0
W
RESET:
15
14
13
12
R
WT
W
RESET:
0
0
0
0
WT — Watchdog Time-Out
The six-bit WT field contains the time-out value. These bits are reloaded into the
watchdog timer when it has been serviced. After reset, write WT before enabling the
watchdog. The value in WT is loaded into the watchdog counter after running the ser-
vice routine as well as on enabling the watchdog timer.
MOTOROLA
9-10
Freescale Semiconductor, Inc.
NOTE
27
26
25
24
0
0
0
0
11
10
9
8
0
0
0
0
Figure 9-10 Watchdog Control Register
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
23
22
21
20
0
0
0
0
7
6
5
4
0
0
0
0
WSTP WDE WDBG WDZE
1000101C
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
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