Instruction Address Fifo Buffer (Pc Fifo); Once Pc Fifo - Motorola M-CORE MMC2001 Series Reference Manual

16.12 Instruction Address FIFO Buffer (PC FIFO)

To ease debugging activity and keep track of program flow, a first-in-first-out (FIFO)
buffer stores the addresses of the last eight instruction change-of-flow prefetches that
were issued.
The FIFO is implemented as a circular buffer containing eight 32-bit registers and one
3-bit counter. All the registers have the same address, but any read access to the
FIFO address causes the counter to increment and point to the next FIFO register.
The registers are serially available to the external command controller through the
common FIFO address. Figure 16-11 shows the block diagram of the PC FIFO.
MOTOROLA
16-20
Freescale Semiconductor, Inc.
Instruction Fetch Address
PC FIFO Register 0
PC FIFO Register 1
PC FIFO Register 2
PC FIFO Register 3
PC FIFO Register 4
PC FIFO Register 5
PC FIFO Register 6
PC FIFO Register 7
PC FIFO Shift Register
Figure 16-11 OnCE PC FIFO
OnCE™ DEBUG MODULE
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Circular
Buffer
Pointer
TCK
TDO
REFERENCE MANUAL
MMC2001