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OCMR — OnCE Command Register
BIT 7
R/W
GO
R/W — Read/Write Command
The R/W bit specifies the direction of data transfer.
0 = Write the data associated with the command into the register specified by
the RS field.
1 = Read the data contained in the register specified by the RS field.
GO — Go Command
When the GO bit is set, the device executes the instruction that resides in the IR reg-
ister in the CPUSCR. To execute the instruction, the processor leaves debug mode,
executes the instruction, and if the EX bit is cleared, returns to debug mode immedi-
ately after executing the instruction. The processor resumes normal operation if the
EX bit is set. The GO command is executed only if the operation is a read/write to
either CPUSCR or "No register selected". Otherwise, the GO bit is ignored. The pro-
cessor leaves debug mode after the TAP controller update-DR state is entered.
0 = Inactive (no action taken)
1 = Execute instruction in IR
EX — Exit Command
When the EX bit is set, the processor leaves debug mode and resumes normal oper-
ation until another debug request is generated. The exit command is executed only if
the Go command is issued, and the operation is a read/write to CPUSCR or read/
write to "No register selected". Otherwise the EX bit is ignored. The processor exits
debug mode after the TAP controller update-DR state is entered.
0 = Remain in debug mode
1 = Leave debug mode
RS — Register Select
The register select bits define the source or destination register for the read or write
operation, respectively. Table 16-1 shows OnCE register addresses.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
6
5
4
EX
Figure 16-4 OnCE Command Register
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
3
2
1
RS
BIT 0
MOTOROLA
16-7
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