Table of Contents
Advertisement
RLD — Counter Reload Control
This bit controls whether the value contained in the modulus latch is reloaded into the
counter when the counter reaches a count of zero or whether the counter rolls over
from zero to 0xFFFF
0 = Counter rolls over to 0xFFFF
1 = Counter is reloaded from the modulus latch
EN — PIT Enable
This bit controls the PIT enable function
0 = PIT is disabled
1 = PIT is enabled
9.6.6 PIT Data Register (ITDR)
On a write, the data becomes the new timer modulus. This value is retained and is
used at the next and all subsequent reloads until changed by another write to ITDR.
This value is initialized to the maximum count of 0xFFFF on reset. On a read, the
ITDR returns the value written in the modulus latch. The only way to change the value
of the count directly is to preload a modulus with the OVW bit set to one. The counter
value can be read from the PIT alternate data register.
Access this register with 32-bit loads and stores only.
ITDR — PIT Data Register
31
30
29
28
R
0
0
0
0
W
RESET:
15
14
13
12
R
W
RESET:
1
1
1
1
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
27
26
25
24
0
0
0
0
11
10
9
8
PIT DATA
1
1
1
1
Figure 9-17 PIT Data Register
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
23
22
21
20
0
0
0
0
7
6
5
4
1
1
1
1
10001028
19
18
17
16
0
0
0
0
3
2
1
0
1
1
1
1
MOTOROLA
9-15
Advertisement
Table of Contents
