Siemens ET 200SP Manual page 91

Technology module tm pulse 2x24v
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Configuring/address space
4.4 On/Off delay mode
Byte
offset
Bit 7
relative
to start
address
Channel
0/1
↓ ↓
9
21
10
22
11
23
Note
Channel 1 is only available in two-channel operation of the module.
Control bit/value
OUTPUT_VALUE
SLOT
MODE_SLOT
LD_SLOT
SET_DQA
SET_DQB
90
Bit 6
Bit 5
Reserved
Explanations
You specify the On delay with this value.
Value range:
On delay in μs: 0 to 85000000
If the setting is outside the value range, the ERR_OUT_VAL feedback bit is set and the last
valid On delay is used.
You specify the load value with this value.
Value range:
Off delay in μs: 0 to 85000000
You specify whether to apply a change once or cyclically with MODE_SLOT.
Invalid values trigger setting of feedback bit ERR_LD (when MODE_SLOT = 0) or
ERR_SLOT_VAL (when MODE_SLOT = 1).
You specify whether you want to apply a change in SLOT once or cyclically with this bit.
0 means: As soon as you write the value 3
SLOT is applied once and kept until the next change. A change using SLOT takes effect on the
next falling edge at DIn.0. After a restart of the module, the value is overwritten with the value
set in the hardware configuration.
1 means: When you write the value 19
from SLOT in each case is applied cyclically. A change using SLOT takes effect on the next
falling edge at DIn.0.
You specify the meaning of the value in SLOT with this load request:
0000
means: No action, idle
B
0011
means: Off delay in μs:
B
Values not listed are invalid and trigger setting of feedback bit ERR_LD (when MODE_SLOT =
0) or ERR_SLOT_VAL (when MODE_SLOT = 1).
You use this bit to set digital output DQn.A when TM_CTRL_DQ and SET_DQB are set to 0.
You use this bit to set digital output DQn.B when TM_CTRL_DQ and SET_DQA are set to 0.
Bit 4
Bit 3
SET_DQB
SET_DQA
Reserved
Reserved
D
D
in the corresponding output byte, the value from
D
in the corresponding output byte, the current value
D
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Bit 2
Bit 1
Reserved
TM_
CTRL_DQ
Manual, 05/2019, A5E35061186-AB
Bit 0
SW_
ENABLE
RES_
ERROR

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