Siemens ET 200SP Manual page 36

Pulse diagram
The following figure shows an example of an output sequence when DIn.0 is being used as a
hardware enable.
Figure 4-2 Example of an output sequence
If you are using the hardware enable, it is combined with the software enable. When the
software enable is active, the output sequence starts at the first rising edge of the hardware
enable. Additional rising edges of the hardware enable during the output sequence are
ignored. If the hardware enable is set and remains set for the duration of the input delay, the
On delay is started and the STS_ENABLE feedback bit is set. As soon as the On delay has
elapsed, the pulse width modulated signal is output with the assigned duty cycle at the
respective digital output DQn.A. The duty cycle is the ratio of pulse duration to period
duration. The output sequence runs continuously, as long as SW_ENABLE is set.
If you are not using a hardware enable, the On delay starts at the rising edge of
SW_ENABLE. The hardware enable is not supported in isochronous mode.
Aborting the output sequence
If you reset the SW_ENABLE control bit, the software enable is deactivated and the current
output sequence is aborted. The last period is not completed. The STS_ENABLE feedback
bit and the digital output DQn.A are reset.
A renewed pulse output is only possible after a restart of the output sequence.
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Manual, 05/2019, A5E35061186-AB
Configuring/address space
4.2 Pulse width modulation PWM mode
35