Siemens ET 200SP Manual page 83

Configuring/address space
4.4 On/Off delay mode
Aborting the output sequence
If you reset the SW_ENABLE control bit, the software enable is deactivated and the current
output sequence is aborted. The STS_ENABLE feedback bit and the digital output DQn.A
are reset.
A renewed pulse output is only possible after a restart of the output sequence.
Minimum pulse duration and minimum interpulse period
The minimum pulse duration and the minimum interpulse period are the minimum pulse
duration and interpulse period that are to be output. Each amounts to 1.5 µs when the high-
speed output (Page 84) is activated and 10 µs when the high-speed output is deactivated.
Pulses and interpulse periods of digital input DIn.0 whose duration is less than the minimum
pulse duration are ignored by the module and are not output at the digital output DQn.A.
The pulse or the interpulse period of DIn.0 is also ignored in the following cases:
● Pulse duration < Input delay
● Pulse duration + Off delay ≤ On delay (ERR_PULSE is set)
● Pulse duration + Off delay + Minimum pulse duration < On delay (ERR_PULSE is set)
● Interpulse period < Input delay
● Interpulse period + On delay ≤ Off delay (ERR_PULSE is set)
● Interpulse period + On delay < Off delay + Minimum interpulse period (ERR_PULSE is
set)
A set ERR_PULSE feedback bit is cleared on the next rising edge at DIn.0.
Retriggering the On delay
In the following case, the module cancels the current On delay and restarts it with the next
rising edge at digital input DIn.0:
On delay > Pulse duration + Interpulse period
The following figure shows an example of the retriggering of the On delay:
Figure 4-7
82
Retriggering the On delay
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Manual, 05/2019, A5E35061186-AB