Siemens ET 200SP Manual page 47

Configuring/address space
4.2 Pulse width modulation PWM mode
P_Sel
I_Sel
D_Sel
Reference value current (mA)
Dead band width (μA)
Manipulated value high limit
(S7 analog value)
Manipulated value low limit
(S7 analog value)
Gain
TI (s)
TD (s)
TM_LAG (s)
The default setting of the controller parameters is chosen conservatively to enable stable
operation. For dynamic valve positioning, you optimize the individual parameters to fit your
plant conditions. In particular, a higher gain factor and a lower integration time lead to faster
reactions to a setpoint change.
Controller cycle time
When dithering is deactivated, the internal cycle time of the controller corresponds to the
PWM period duration. When dithering is active, the internal cycle time of the controller
corresponds to the dithering period duration.
Resetting the PID controller
The internal data of the controller is reset in the following cases:
● SW_ENABLE control bit is reset
● New parameter data record is sent to module
Further information
You can find further information on PID controllers in the PID Control
(https://support.industry.siemens.com/cs/ww/en/view/108210036) function manual, e.g. in
the CONT_C section.
46
Enable proportional action of the PID algorithm
Enable integral action of the PID algorithm
Enable derivative action of the PID algorithm
Maximum value as reference value for the current setpoint. The recommended setting is
the value of the load current that is measured when current control is deactivated and the
duty cycle is 100%.
Deviation of the output current from the current setpoint within which no correction takes
place. The deviation refers to a range above and below the current setpoint.
High control limit
Low control limit
Gain factor for P-component of the PID algorithm
Integration time; length of time used by the I-component of the PID algorithm.
If TI is less than the controller cycle time, TI is set internally to the value of the cycle time.
Derivative action time; length of time used by the D-component of the PID algorithm.
If TD is less than the controller cycle time, TI is set internally to the value of the cycle time.
Time lag of the D-component of the PID algorithm.
If TI is less than half the controller cycle time, TI is set internally to half the value of the
cycle time.
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Manual, 05/2019, A5E35061186-AB