Appendix B: Xilinx Constraints File; Overview - Xilinx EK-U1-VCU128-G-J User Manual

Xilinx Constraints File

Overview

The Xilinx ® design constraints (XDC) file template for the VCU128 board provides for designs
targeting the VCU128 evaluation board. Net names in the constraints listed correlate with net
names on the latest VCU128 evaluation board schematic. Identify the appropriate pins and
replace the net names with the net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more information.
The FMCP connector J18 (HSCP) is connected to 1.8V (nominal) VADJ banks 70 and 71. Because
different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely
defined by each customer.
IMPORTANT! See
UG1302 (v1.1) April 21, 2021
VCU128 Board User Guide
VCU128 board documentation

Appendix B: Xilinx Constraints File

for the XDC file.
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Appendix B
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