Appendix B: Xilinx Design Constraints; Overview - Xilinx VCK190 Series User Manual

Xilinx Design Constraints

Overview

The Xilinx ® design constraints (XDC) file template for the VCK190 board provides for designs
targeting the VCK190 evaluation board. Net names in the constraints listed correlate with net
names on the latest VCK190 evaluation board schematic. Identify the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more information.
The HSPC FMCP connectors J51 and J53 are connected to ACAP U1 banks powered by the
variable voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC
bank I/O standards must be uniquely defined by each customer.
IMPORTANT! See the
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
VCK 190 board documentation

Appendix B: Xilinx Design Constraints

Appendix B
("Board Files" check box) for the XDC file.
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