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or 32-pin ROM Modules.
24-, 28-,
from the particular ROM Module
appropriate line
Self Test Assembly
The Self Test Assembly schematic diagram
The latched address lines from the Pod processor pass through protection
(Al,
hybrids
assemblies
on J1
Sync Module Connector). The
the ROM Modules
and
passed to readable data
are
Module or Emulation
RAM
The RAM Module schematic diagram
The RAM Module contains two separate RAM chips
emulation RAM
RAM
has a
communicate with the Pod processor while
ROM Modules.
The data lines from the banks of RAM
or U4), so that whichever bank is communicating with the Pod processor
sends data through the selected buffer
bank passes data through a pair of muxes
terminating resistor package
data bus
goes
ROM data
lines.
Personality Module
The Personality Module contains
The Personality Module is processor dependent,
and
one
PAL.
processor, have extra inverters for
used for the clock
delays, thereby avoiding timing skew problems).
allow for swapping between
wired to
board for a 27C256
the
Jumpers
W3 and
either high or low upon the timed receipt of
(OVDRVCH?3)
OVDRV-OUT signal
the
The inputs to
Module, request reset (REQRESET), overdrive channel
either high or low), the sync control
ROMISEL (which is the active bus cycle clock from the ROM Modules).
The outputs from the PAL
(i.e., 24-, 28-,
fail
J2 for
the power
on
A2,
drive various pins
and A3) and
ZIF socket), J2
(a
32-pin
lines
received at these sockets, pass through
are
lines.
RAM
and U6
emulation RAM
is
A,
of address
separate
set
and
(Z1),
through the buffers
on the
user-serviceable parts.
no
'Some
Personality Modules,
others were used
line, and
27C256 or
a
ROM).
W4 determine the polarity for driving channel
is installed
'W3
request.
is
processor dependent.
PAL include the
the
the
are
The adapters also take the power pin
or 32-pin)
detector
line.
shown
is
in
Figure
either the ROM Module
on
40-pin ZIF socket), or J4 (the
(a
that are output from the Sync Module or
is shown in
Figure
5-4.
(US and
Each bank
B.
This allows one bank to
lines.
other bank is used
the
a
pair of data buffers
to
one
go
of
to the Pod data
back
(U7 and US),
ROM Module data
to the
ROM Module
and
always has one PROM
but
the one for the 80286
such as
of
input lines (one inverter
the
some
other inputs to match
on
Jumpers
27C512 ROM (normally W2
a
overdrive channel
the
overdrive
low.
to
input channels from the
seven
lines
(PSYNCCTL1,
clock (which depends
sync
9132A Service
run it to the
and
2-13.
5-2.
the
hybrids,
2-14.
is
U6).
US
of
emulation
the
by
(U3
The other
lines.
through a back-
This
bus.
out to the UUT
2-15.
is
and W2
W1
is
3 (CH3)
3
The polarity of
Sync
overdrive
3 (to
and
and
2,
3),
the
on
sync
2-15
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